TL; DR
- Huawei has introduced a new semiconductor framework called the Tau (τ) Scaling Law alongside a new LogicFolding chip architecture that it says could achieve 1.4nm-equivalent transistor density by 2031.
- Instead of relying purely on smaller manufacturing nodes and EUV lithography, Huawei says it is focusing on architecture-level optimizations, signal delays, and system efficiency to bypass current hardware restrictions.
- The first commercial Kirin smartphone chips using LogicFolding are expected later in 2026.
Huawei has officially unveiled a new semiconductor roadmap that could become one of the company’s biggest long-term technology bets yet. During the IEEE International Symposium on Circuits and Systems (ISCAS 2026) in Shanghai, Huawei semiconductor chief He Tingbo introduced what the company calls the “Tau (τ) Scaling Law,” along with a new chip architecture named LogicFolding.
According to Huawei, this new approach could eventually allow the company to achieve transistor density levels equivalent to 1.4nm-class chips by 2031, despite ongoing US sanctions limiting access to advanced EUV lithography systems. For reference, TSMC currently plans to begin mass production of actual 1.4nm chips around 2028.
What Is the Tau Scaling Law?
For decades, semiconductor progress has mostly followed Moore’s Law, where chipmakers improve performance by physically shrinking transistor sizes generation after generation.
Huawei says the Tau Scaling Law takes a different path. Instead of focusing entirely on shrinking transistors geometrically, the company wants to optimize overall chip efficiency through signal delay reductions, architectural redesigns, and system-level performance improvements over time.
Alongside this, Huawei introduced LogicFolding, a proprietary chip design architecture that reportedly improves transistor density by around 55% compared to more traditional layouts while also improving efficiency.
Simply put, Huawei is trying to squeeze significantly more performance and density from existing manufacturing capabilities rather than depending entirely on next-generation fabrication equipment.
Designed Around Current Sanctions
One of the biggest reasons behind this strategy is the continued US restriction on advanced semiconductor manufacturing equipment. Since 2019, Huawei has faced heavy limitations around accessing cutting-edge EUV lithography systems used for modern 3nm, 2nm, and future manufacturing nodes.
Right now, China’s most advanced large-scale commercial manufacturing capability through SMIC is generally believed to sit around the 7nm level.
Huawei says Tau Scaling and LogicFolding allow it to reduce reliance on pure node shrinking while still pushing toward higher-density, higher-performance chips over the next several years.
The company described the approach as both “feasible and affordable,” though it has not yet shared independent third-party benchmarks or validation data.
First Kirin Chips Arrive Later This Year
Huawei says it has already designed and mass-produced 381 chips over the last six years using parts of this new design philosophy. The first fully LogicFolding-based commercial chips are expected to arrive later in 2026 inside upcoming Kirin smartphone processors, likely debuting with the Huawei Mate 90 series.
After that, Huawei plans to scale the architecture further into its Ascend AI processors and large-scale AI data-center hardware by 2030.
Right now, these are still long-term claims rather than proven commercial results. Real-world performance, thermals, efficiency, manufacturing scalability, and software optimization will ultimately decide whether Huawei’s approach works at scale.
Still, the announcement highlights how aggressively Huawei continues pushing toward semiconductor self-reliance despite ongoing sanctions around advanced chip manufacturing equipment.
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